Skiron: Experiments in CPU Design in D

Mithun Hunsur
May 6 @ 4:30 PM

Duration: 50 minutes
Talk type: Presentation
Level: Intermediate to Advanced
Slides: SlideShare · PDF

Abstract:  When designing a CPU, many considerations need to be taken into account: from hardware constraints to instruction set flexibility, building an architecture worthy of use requires compromise. This talk details the effective use of D and its features, such as metaprogramming, to enable rapid development with equally rapid performance for Skiron: a CPU design and implementation focused on examining the impact of particular design decisions on flexibility and performance.

Skiron is a flexible 32-bit RISC and MIPS-inspired architecture designed for the sole purpose of evaluating potential compromises in CPU design with a minimal time investment in making changes. To this end, the tools involved in the ecosystem – the reference simulator, assembler, disassembler, and documentation – needed to be built around the principle of rapid iteration.

As a result, D was selected as the implementation language: its unique blend of features places it in an ideal place for Skiron, especially with regards to ensuring that changes in design will be reflected across the entire ecosystem. This is accomplished through extensive use of metaprogramming, D-exclusive features, the excellent standard library, and much more.

Areas investigated in this talk will include, but not be limited to:

Speaker Bio: During the day, Mithun Hunsur is an undergraduate student at Monash University – but during the nights and the weekends, he’s a prolific systems programmer and reverse engineer working on exploring the far reaches of the technologies he works with on a daily basis. Since 2013, he has been utilising D in a variety of projects, both internal and external, in order to maximise development speed while keeping performance characteristics from other systems languages. As part of his efforts to support the wider D ecosystem, he has submitted pull requests to druntime and Phobos, and has assisted in improving the performance of exception handling in LDC. He is currently situated in Melbourne, Australia.

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