DHDL: The D Hardware Description Language

Luís Marques
May 4 @ 12:00

Duration: 50 minutes
Talk type: Presentation
Level: Beginner
Slides: PDF
Presentation Video
Demo Video


With the slowdown of Moore's law, there has been an increased interest in augmenting the computing power of the CPUs found in data centers with more parallel and energy-efficient alternatives, such as GPUs, FPGAs and ASICs. While replacing general-purpose CPUs with specialized hardware accelerators can provide order-of-magnitude improvements in computing power and energy efficiency, designing custom hardware is still a daunting task, impaired by archaic tools and a culture that has failed to appreciably raise the level of abstraction.

This talk presents DHDL, a D language extension and library for constructing digital hardware. By leveraging the strong modeling power of D, DHDL facilitates the design of parameterized hardware blocks. This flexibility promotes reuse, thereby increasing the hardware designer's productivity; it also decreases the rigidity of the designs, allowing for an easier exploration of the design-space or the accommodation to new requirements.

The talk will go over several topics that will help the audience members start to design their own hardware accelerators or FPGA-based embedded systems:

These topics will be presented in the context of a complete system, including:

  1. IO: How to use common IO interfaces (e.g. UARTs), such that you can:
    • Get the data in and out of your hardware accelerators
    • Communicate with the outside world in your embedded systems
  2. Memory: How to use different types of memory, including:
    • FPGA block memory
    • FPGA distributed memory
    • Synchronous DRAM
  3. Computation:
    • Brief overview of architecture and ISA design
    • Microarchitecture and achieving timing closure

Speaker Bio:

I am a generalist programmer, with a good grasp of computer architecture and distributed systems. I started using D early in its life, but I became especially interested in the language when ranges and range-based algorithms were introduced. These STL-inspired facilities made significant progress on a promise that object-oriented programming failed to deliver, and which the STL only delivered to a limited extent: the design and employment of reusable components.

By training I am a software engineer. By night I wear a cape and dabble in hardware design. A few years ago I bought an FPGA and taught myself hardware design. While FPGAs are super exciting, I found that VHDL and Verilog can sap all the joy out of hardware design. As part of my search for alternatives I found Chisel. While Chisel aimed to do for hardware what D tries to achieve with its design by introspection (create generic yet efficient building blocks), I found the usability of Chisel to suffer due to its life as Scala DSL.

I have stated before that "whenever possible I choose D for the task -- even for hardware design". This is my attempt to make good on that promise; to bring the Chisel model of hardware design to D, and all the modeling power it has to offer.